Data processing system

ABSTRACT

The invention relates to a processing system comprising a calculation device comprising at least one calculation unit ( 13 ), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the switching system, the storage device comprises several banks of registers ( 21, 22 ) for storing words, the switching system comprises at least one switching device ( 24 ) associated with each bank of registers and the calculation units exchange a word with a bank of registers by means of the associated switching device.

FIELD OF THE INVENTION

The present invention relates to a processing system comprising acalculation unit, a storage device and a system for switching betweenthe storage device and the calculation unit.

The invention finds an application, for example, in a video dataprocessing system. For example, an image reproduction processor canconstitute such a video data processing system. This image reproductionprocessor can be included, for example, in a decoder, a decodingreceiving device for television (a “Set Top Box”) or a television.

BACKGROUND OF THE INVENTION

Many processing systems comprise one or more calculation units intendedto perform operations on data. These calculation units can exchangewords comprising the data with a storage device in which said words arestored. To do this, a switching system (a “crossbar system”) is used inorder in particular to direct the words coming from the storage deviceto a suitable calculation unit. The publication “Architecture andImplementation of a High-Definition Video Co-Processor for DigitalTelevision Applications” by Santanu Dutta et al., published in January2000, describes an example of such a processing system.

This processing system comprises a bank of registers constituting thestorage device and comprising register reading ports and registerwriting ports, calculation units comprising calculation unit input portsand calculation unit output ports, and a reading and writing switchingsystem comprising a reading switching system and a writing switchingsystem. An exchange of words can be effected from a register readingport to a calculation unit input port, by means of the reading switchingsystem; this is then a reading. An exchange of words can also beeffected from a calculation unit output port to a register writing port,by means of the writing switching system. This is then a writing.

The term “calculation unit port” will hereinafter be appliedindifferently to a calculation unit input or output port, “registerport” to a register reading or writing port and “switching system” to areading or writing switching system. In addition, the term “exchange”applies to a reading or writing of words.

In such a processing system, the switching system is implemented bymeans of multiplexers. The size of the switching system depends on thenumber of multiplexers used. The number of multiplexers depends on thenumber of register ports and calculation unit ports between which wordsmay be exchanged, and the size of the words exchanged. In thisprocessing system, the size of the words exchanged is large, and thewords can be exchanged between all the register ports and all thecalculation unit ports, by means of the switching system.

FIG. 1 illustrates a processing system according to the state of theart. Such a processing system comprises a storage device 10, a readingswitching system 11, a writing switching system 12, and first, second,third and fourth calculation units 13 to 16. The storage device 10comprises six register reading ports, for example rrp1 and rrp6, andfour register writing ports, for example wrp1 and wrp4. The calculationunits comprise calculation unit input ports, for example iup1 and iup2,and calculation unit output ports, for example eup5.

In this example, the words exchanged are words of P bits. Let it beassumed that the first calculation unit 13 wishes to read a data itemstored in the storage device 10, on its calculation unit input portrup1. A control device, not shown in FIG. 1, indicates to the storagedevice 10 that it must send this data item over one of its readingports, for example the port rrp1. This data item is then sent to thereading switching system 11, which is responsible for sending the dataitem to the calculation unit input port rup1. To do this, the readingswitching system 11 comprises multiplexers. The control device sendscontrol signals to the multiplexers, in order to direct the data item tothe calculation unit input port iup1.

In such a processing system, all the register reading ports areconnected to all the calculation unit input ports by means of thereading switching device 11. The expression “two ports are connected”means that an exchange of words is possible between these two ports. InFIG. 1, only a few connections have been shown, for reasons of clarity.If:

-   -   the number of register reading ports is termed m;    -   the number of calculation unit input ports is termed n, and    -   the number of bits of the words exchanged is termed P,    -   the number of multiplexers of the reading switching device is        n(m−1)P.

For the writing switching device, the functioning is the same. If:

-   -   the number of calculation unit output ports is termed m′;    -   the number of register writing ports is termed n′, and    -   the number of bits of the words exchanged is termed P,    -   the number of multiplexers of the writing switching device is        n′(m′−1)P.

The number of multiplexers therefore depends in particular on the numberof bits of the words exchanged. However, the words exchanged have a sizeof P bits, whilst certain calculation units perform certain operationson data of a lesser size, for example P/N bits. When a calculation unitwishes to read a data item P/N bits, the storage device sends to it aword of P bits comprising this data item. Consequently, during such anexchange, (N−1)P/N bits are not used by the calculation unit.

This results in the size of the switching system being large. Thispresents a drawback, since the switching system is bulky. Because ofthis, the number of calculation units and calculation unit ports islimited, since the switching system cannot occupy more than a predefinedsurface area.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to propose a processing system in whichthe size of the switching system is reduced.

A processing system according to the invention and as defined in theopening paragraph is characterized in that:

-   -   the storage device comprises several banks of registers;    -   the switching system comprises at least one switching device        associated with each bank of registers;    -   the calculation unit is able to communicate with at least two        banks of registers by means of the associated switching devices.

According to the invention, the words stored in the banks of registershave a lesser size than in the state of the art, for example P/N bits.The data on which the calculation units can perform operations havesizes of P/N, 2P/N, . . . (N−1)P/N or P bits for example. When acalculation unit wishes to read a data item of P/N bits, a first bank ofregisters comprising this data item sends to it the corresponding wordof P/N bits, by means of the switching device (the “crossbar”) which isassociated with it. When it wishes to read a data item of 2P/N bits, thefirst bank of registers comprising the first P/N bits of this data itemsends to it the corresponding word over one of its calculation unitports, by means of the switching device associated with this first bankof registers, and a second bank of registers comprising the followingP/N bits of the data item sends to it the corresponding word over one ofits other calculation unit ports, by means of the switching deviceassociated with this second bank of registers. A similar reasoningapplies when the calculation unit wishes to read a data item of agreater size.

By virtue of the invention, certain banks of registers may have a lessernumber of register ports than the storage device of the state of theart. This will be described in further detail hereinafter. Likewise, itis possible to omit certain connections between certain register portsand certain calculation unit ports. This will also be described in moredetail hereinafter. Consequently it is possible to use a lesser numberof multiplexers and thus reduce the size of the switching system.

In a preferred embodiment of the invention, the calculation unitcomprises at least one port and the switching system also comprises acommon switching device by means of which the port of the calculationunit can communicate with several registers. According to thisembodiment, one and the same calculation unit port is able to exchangewords with several registers.

In an advantageous embodiment of the invention, the calculation unitcomprises at least one port, said port being able to communicate with asingle bank of registers. According to this embodiment, the exchange ofa word between a calculation unit port and a bank of registers is madesolely by means of the switching device associated with this bank ofregisters. This embodiment makes it possible to dispense with aswitching device common to several banks of registers.

In this way, the number of multiplexers used in the switching system isreduced. Thus the size of the switching system is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be further described with reference to examples ofembodiments shown in the drawings to which, however, the invention isnot restricted.

FIG. 1 is a block diagram illustrating characteristics of a processingsystem according to the state of the art;

FIG. 2 is a block diagram illustrating characteristics of a processingsystem according to the invention;

FIG. 3 a illustrates an example embodiment of a processing systemaccording to the state of the art and FIG. 3 b illustrates a processingsystem according to the invention for replacing the processing system ofFIG. 3 a;

FIG. 4 illustrates an example of a processing system according to anadvantageous embodiment of the invention;

FIGS. 5 to 11 illustrate an example of the use of a processing systemaccording to the invention in an image reproduction processor.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2 illustrates an example of a processing system according to theinvention. Such a processing system comprises a first bank of registers21, a second bank of registers 22, a third bank of registers 23, a firstswitching device 24, a second switching device 25, a third switchingdevice 26, a first common switching device 27, and the first, second,third and fourth calculation units 13 to 16.

The switching devices depicted in FIG. 2 are reading switching devices.FIG. 2 therefore illustrates a data reading by the calculation units 13to 16. The invention applies in the same way to a writing of data fromthe calculation units to the banks of registers, that is to say forwriting switching devices.

The first, second and third banks of registers 21 to 23 store smallerwords than in the state of the art, for example words of P/N bits. Forthis example, it is considered that P is equal to thirty-six and N isequal to three. The words exchanged are therefore words of twelve bits.Let it be assumed that the third calculation unit 15 wishes to read adata item of thirty-six bits in the storage device consisting of thethree banks of registers 21 to 23. The first twelve bits of this dataitem are stored in the first bank of registers 21, the following twelvebits in the second bank of registers 22 and the last twelve bits in thethird bank of registers 23. The third calculation unit comprises threecalculation unit ports iup7, iup8 and iup9.

The first bank of registers 21 sends the first twelve bits of the dataitem to the first switching device 24, which sends these first twelvebits to the first common switching device 27, which sends these firsttwelve bits to the port iup7. The second bank of registers 22 sends thefollowing twelve bits to the second switching device 25, which sendsthese following twelve bits to the first common switching device 27,which sends these following twelve bits to the port iup8. The third bankof registers 23 sends the last twelve bits of the data item to the thirdswitching device 26, which sends these last twelve bits to the firstcommon switching device 27, which sends these last twelve bits to theport iup9.

It is also possible that a calculation unit, for example the secondcalculation unit 14, may wish to read simultaneously three data items oftwelve bits, or one data item of twelve bits and one data item oftwenty-four bits. In these two cases, no word is read in the third bankof registers 23. Consequently, if the data items read frequently have asize of twelve or twenty-four bits, it is possible to reduce the numberof register ports of the second bank of registers 22 and of the thirdbank of registers 23, compared with the number of register ports of thestate of the art.

Consider an example where the calculation units 13 to 16 wish to readsimultaneously 4 data items of twelve bits, one data item of twenty-fourbits and one data item of thirty-six bits.

The storage device 10 of the state of the art described in FIG. 1 mustthen send six words of thirty-six bits. It therefore requires sixregister ports of thirty-six bits.

With the processing system of FIG. 2, where the first bank of registers21 has six register ports, the second bank of registers 22 has fourregister ports and the third bank of registers 23 has two registerports, it is possible, for the storage device consisting of the banks ofregisters 21 to 23, to send simultaneously four data items of twelvebits, one data item of twenty-four bits and one data item of thirty-sixbits. Thus, with a number of register ports, with certain banks ofregisters, less than the number of register ports of the state of theart, it is possible to send simultaneously the same data items as in thestate of the art. Consequently, by virtue of the invention, it ispossible to reduce the number of ports of certain banks of registers.

Naturally, with the processing system of FIG. 2, it is not possible tosend simultaneously six data items of thirty-six bits. However, such asituation is rare or even non-existent in many processing systems of thestate of the art, which makes it possible to implement the invention inorder to replace the majority of processing systems according to thestate of the art.

Consequently, provided that, amongst data which are to be exchangedsimultaneously, some have a size less than thirty-six bits, it ispossible to reduce the number of register ports of at least one bank ofregisters, compared with the number of register ports of the state ofthe art.

In FIG. 2, only a few connections have been depicted for reasons ofclarity. For example, all the register ports can be connected to all thecalculation unit ports. If:

-   -   the number of register ports of the first bank of registers 21        is termed m1;    -   the number of register ports of the second bank of registers 22        is termed m2;    -   the number of register ports of the third bank of registers 23        is termed m3;    -   the total number of calculation unit ports is termed n;    -   the number of multiplexers of the switching system, consisting        of the three switching devices 24 to 26 and the first common        switching device 27, is equal to: n(m1+m2+m3−1)P/3.

Since (m1+m2+m3) is less than (3m−2), as is the case in the processingsystem in FIG. 2, the number of multiplexers in the switching system isless than the number of multiplexers required in the state of the artdescribed in FIG. 1. Consequently the invention makes it possible toreduce the size of the switching system.

In order to reduce the size of the switching system further, it is alsopossible to omit certain connections between certain register ports andcertain calculation unit ports. This is because, in the example citedabove, the third bank of registers 23 never exchanges data with thecalculation unit ports iup7 and iup8 of the third calculation unit 15.Consequently it is possible to omit the connections between the registerports of the third bank of registers 23 and the calculation unit portsiup7 and iup8, that is to say four connections. If X connections in allare omitted, the number of multiplexers in the switching system is equalto: [n(m1+m2+m3−1)−X]P/3.

Consequently the processing system according to the invention makes itpossible to reduce the size of the switching system in two ways. Thefirst way consists of taking, for certain banks of registers, a numberof ports less than the number of ports of the storage device of thestate of the art. The second way consists of omitting certainconnections between certain register ports and certain calculation unitports. These two ways of reducing the size of the switching system canbe implemented separately or conjointly.

It should be noted that the banks of registers according to theinvention do not necessarily all have the same size. For example, inorder to replace the storage device 10 of the state of the art, whenthis storage device 10 stores words of thirty-six bits, it is possibleto take a bank of registers of twenty-four bits and a bank of registersof twelve bits.

It should be noted that a data item of twelve bits is not necessarilystored in the first bank of registers 21. For example, data items oftwelve bits can be stored either in the first bank of registers 21, thesecond bank of registers 22 or the third bank of registers 23. In thiscase, it is possible to reduce the number of the ports of each of thethree banks of registers 21 to 23, as stated in FIGS. 3 a and 3 b.

FIG. 3 a illustrates an example of an implementation of a processingsystem according to the state of the art. This processing systemcomprises a storage device 30 having three register ports, a switchingdevice 31 and a fifth calculation unit 32.

The data to be exchanged are data of twelve bits, which correspond tored, green and blue components of a pixel of an image. These data arestored in the form of words of twelve bits. The fifth calculation unit32 needs to read simultaneously the red component, the green componentand the blue component, but does not need to read simultaneously threered components for example. Each of the ports of the storage device 30can send either a red, a green or a blue component. The switching device31 therefore comprises, in this example, 3*(3−1)*12=72 multiplexers.

FIG. 3 b illustrates an example of an embodiment of a processing systemaccording to the invention, for replacing the processing system of FIG.3 a. This processing system according to the invention comprises afourth bank of registers 33, a fifth bank of registers 34, a sixth bankof registers 35, a fourth switching device 36, a fifth switching device37, a sixth switching device 38, a second common switching device 39 andthe fifth calculation unit 32.

The banks of registers 33 to 35 each comprise a twelve-bit port. Thefifth calculation unit 32 comprises three twelve-bit ports. The redcomponent is stored in the fourth bank of registers 33, the greencomponent is stored in the fifth bank of registers 34 and the bluecomponent is stored in the sixth bank of registers 35. Consequently,with the processing system of FIG. 3 b, the fifth calculation unit 32can read simultaneously the red, green and blue components. Theprocessing system of FIG. 3 b can therefore replace the processingsystem of FIG. 3 a.

If it is assumed that words can be exchanged between all the registerports and all the calculation unit ports, the switching systemconsisting of the fourth switching device 36, the fifth switching device37, the sixth switching device 38 and the second common switching device39 comprises 3*(3−1)*12=72 multiplexers, that is the same number as inthe state of the art consisting of the processing system of FIG. 3 a.

However, it has been seen that the fifth calculation unit 32 needs toread simultaneously the red component, the green component and the bluecomponent, but does not need to read simultaneously three red componentsfor example. Consequently it is possible to omit a large number ofconnections. For example, it is possible to omit the connections betweenthe register ports of the fifth and sixth banks of registers 34 and 35and a calculation unit port of the fifth calculation unit 32, that is tosay one of the calculation unit ports of the fifth calculation unit 32can read only red components. This therefore makes it possible to reducethe size of the switching system compared with the switching system 31of FIG. 3 a.

It should be noted that, in the example in FIG. 3 b, the banks ofregisters 33 to 35 have only one register port. The switching devices 36to 38 therefore have no multiplexers. Consequently a switching deviceaccording to the invention can comprise one or more multiplexers, or canbe composed solely of physical links, for example wires.

Moreover it possible, as will be seen in more detail in FIG. 4, toassociate each port of the fifth calculation unit 32 with a given bankof registers. For example, it is possible to connect the first port ofthe fifth calculation unit 32 to the fourth bank of registers 34, thesecond port of the fifth calculation unit 32 to the fifth bank ofregisters 35 and the third port of the fifth calculation unit 32 to thesixth bank of registers 36. In this way it is possible to dispense withthe second common switching device 39.

FIG. 4 illustrates a processing system according to an advantageousembodiment of the invention. Such a processing system comprises thefirst, second and third banks of registers 21 to 23, the first, secondand third switching devices 24 to 26, and the first, second, third andfourth calculation units 13 to 16. In FIG. 4, all the connectionsnecessary to the functioning of this processing system between theregister ports and the calculation unit ports have been depicted. Inthis advantageous embodiment, a calculation unit port can exchange wordswith only one bank of registers. For example, the port iup7 of the thirdcalculation unit 15 can exchange words only with the register ports ofthe first bank of registers 21.

If each calculation unit port can exchange words with only one bank ofregisters, as is the case in FIG. 4, it is possible to omit the commonswitching device of FIG. 2, which in particular reduces the complexityof the processing system.

FIGS. 5 to 11 illustrate an example of the use of a processing systemaccording to the invention in an image reproduction processor. Thereexist various formats for a display of video data. For example, anAmerican digital television standard ATSC defines eighteen differentbroadcasting formats, such as the standard format where an imagecomprises 480 lines each of 720 pixels, or the high-definition format inwhich an image comprises 1080 lines each of 1920 pixels. When the videodata are broadcast to the high-definition format, it is necessary toconvert them to the standard format in order to be able to display themon a television whose screen is not compatible with the high-definitionformat. An image reproduction processor makes it possible in particularto make such a conversion.

FIG. 5 illustrates a polyphase filter used in such an image reproductionprocessor. A polyphase filter of this type calculates output valuesPIXOUT of pixels from input values PIXIN of pixels and coefficientsCOEF. If five values of input pixels P1, P2, P3, P4, P5 are considered,and four coefficients c1, c2, c3 and c4, the polyphase filter calculatesthe value P of an output pixel defined by: P=c1(P2−P1)+c2(P3−P2)+c3(P4−P3)+c4(P5−P4)

FIGS. 6 to 11 illustrate processing steps performed by a processingsystem according to the invention in order to use such a polyphasefilter. A processing system of this type comprises a seventh bank ofregisters 601, an eighth bank of registers 602, a ninth bank ofregisters 603, a tenth bank of registers 604, a seventh readingswitching device 605, a seventh writing switching device 606, an eighthreading switching device 607, an eighth writing switching device 608, aninth reading switching device 609, a ninth writing switching device610, a tenth reading switching device 611, a sixth calculation unit 612,a seventh calculation unit 613, an eighth calculation unit 614, a ninthcalculation unit 615, a common reading switching device 616 and a commonwriting switching device 617. For reasons of clarity, the common readingswitching device 616 is not shown in FIGS. 7, 9 and 11 and the commonwriting switching device 617 is not shown in FIGS. 6, 8 and 10.

The values of the input pixels and of the coefficients are coded intwelve bits. The values of the input pixels are stored in the seventhbank of registers 601 and the coefficients are stored in the tenth bankof registers 604.

In a first step illustrated in FIG. 6, the following processings areperformed simultaneously:

-   -   The values of the pixels P1 and P2 are sent to first and second        input ports of the eighth calculation unit 614.

The values of the pixels P2 and P3 are sent to third and fourth inputports of the eighth calculation unit 614.

The values of the pixels P3 and P4 are sent to first and second inputports of the ninth calculation unit 615.

The values of the pixels P4 and P5 are sent to third and fourth inputports of the ninth calculation unit 615.

Next the eighth calculation unit 614 calculates the values (P2−P1) and(P3−P2) and the ninth calculation unit 615 calculates the values (P4−P3)and (P5−P4).

In a second step illustrated in FIG. 7, the following processings areperformed simultaneously:

-   -   The value (P2−P1), which is a data item of twelve bits, is sent        to a first writing port of the seventh bank of registers 601.    -   Likewise the values (P3−P2), (P4−P3) and (P5−P4) are sent to        second, third and fourth writing ports of the seventh bank of        registers 601.

In a third step illustrated in FIG. 8, the following processings areperformed simultaneously:

-   -   The value (P2−P1) and a first coefficient c1, which is a data        item of twelve bits, are sent to first and second input ports of        the sixth calculation unit 612.

The value (P3−P2) and a second coefficient c2 are sent to third andfourth input ports of the sixth calculation unit 612.

The value (P4−P3) and a third coefficient c3 are sent to first andsecond input ports of the seventh calculation unit 613.

The value (P5−P4) and a fourth coefficient c4 are sent to third andfourth input ports of the seventh calculation unit 613.

Next the values c1(P2−P1), c2(P3−P2), c3(P4−P3) and c4(P5−P4) arecalculated by the sixth and seventh calculation units 612 and 613.

In a fourth step illustrated in FIG. 9, the following processings areperformed simultaneously:

-   -   The first twelve bits of c1(P2−P1), which is a data item of        twenty-four bits, are sent to the first writing port of the        seventh bank of registers 601.    -   The last twelve bits of c1(P2−P1) are sent to the first writing        port of the eighth bank of registers 602.    -   The first twelve bits of c2(P3−P2) are sent to the second        writing port of the seventh bank of registers 601.    -   The last twelve bits of c2(P3−P2) are sent to the second writing        port of the eighth bank of registers 602.    -   The first twelve bits of c3(P4−P3) are sent to the third writing        port of the seventh bank of registers 601.    -   The last twelve bits of c3(P4−P3) are sent to the third writing        port of the eighth bank of registers 602.    -   The first twelve bits of c4(P5−P4) are sent to the fourth        writing port of the seventh bank of registers 601.    -   The last twelve bits of c4(P5−P4) are sent to the fourth writing        port of the eighth bank of registers 602.    -   In a fifth step illustrated in FIG. 10, the following        processings are performed simultaneously:    -   The first twelve bits of c1(P2−P1) are sent to the first input        port of the eighth calculation unit 614.    -   The last twelve bits of c1(P2−P1) are sent to the second input        port of the eighth calculation unit 614.    -   The first twelve bits of c2(P3−P2) are sent to the third input        port of the eighth calculation unit 614.    -   The last twelve bits of c2(P3−P2) are sent to the fourth input        port of the eighth calculation unit 614.    -   The first twelve bits of c4(P4−P3) are sent to a fifth input        port of the eighth calculation unit 614.    -   The last twelve bits of c4(P4−P3) are sent to a sixth input port        of the eighth calculation unit 614.    -   The first twelve bits of c5(P5−P4) are sent to a seventh input        port of the eighth calculation unit 614.    -   The last twelve bits of c5(P5−P4) are sent to an eighth input        port of the eighth calculation unit 614.

Next the eighth calculation unit calculates the value:P=c1(P2−P1)+c2(P3−P2)+c3(P4−P3)+c4(P5−P4)

In a sixth step illustrated in FIG. 11, the following processings areperformed simultaneously:

-   -   The first twelve bits of P, which is a data item of twenty-five        bits, are sent to the first writing port of the seventh bank of        registers 601.    -   The following twelve bits of P are sent to the first writing        port of the eighth bank of registers 602.    -   The last twelve bits of P are sent to a first writing port of        the ninth bank of registers 603. These last twelve bits in fact        comprise only one useful data bit.

A processing system such as the one depicted in FIGS. 6 to 11 can beused in an image reproduction processor intended to calculate pixelvalues with a view to displaying these pixels on a screen. Such an imagereproduction processor can be incorporated, for example, in a decoder, aset-top box, a television, a computer central unit or a computer screen.Such an image reproduction processor can be used in a communicationnetwork comprising at least one transmitter able to send signalsrepresenting at least one image, a transmission network and a receiverable to receive said signals.

Use of the verb “comprise” and its conjugations does not exclude thepresence of elements or steps other than those stated in a claim. Use ofthe indefinite article “a” or “an” preceding an element does not excludethe presence of a plurality of such elements.

1. A processing system comprising a calculation unit (13), a storagedevice and a system for switching between the storage device and thecalculation unit, said processing system being characterized in that:the storage device comprises several banks of registers (21, 22); theswitching system comprises at least one switching device (24) associatedwith each bank of registers; the calculation unit is able to communicatewith at least two banks of registers by means of the associatedswitching devices.
 2. A processing system as claimed in claim 1,characterized in that the calculation unit comprises at least one portand the switching system also comprises a common switching device (27)by means of which the port of the calculation unit can communicate withseveral registers.
 3. A processing system as claimed in claim 1,characterized in that: a bank of registers stores words of P/N bits, adata item to be communicated being comprised in one or more words, P andN being integral numbers, N being greater than or equal to 2 and P beinga multiple of N; the calculation unit communicates with i registers forreading or writing a data item of iP/N bits, i being an integer between1 and N.
 4. A processing system as claimed in claim 1, characterized inthat the calculation unit comprises at least one port, said port beingable to communicate with a single bank of registers.
 5. A processingsystem as claimed in claim 4, characterized in that each bank ofregisters stores a data type and the port of the calculation unit isassociated with a data type.
 6. An image reproduction processorcomprising a processing system as claimed in claim
 1. 7. A set-top boxcomprising at least one image reproduction processor as claimed in claim6.
 8. A device comprising at least one screen intended to display imagesand an image reproduction processor as claimed in claim
 6. 9. Acommunication network comprising at least one transmitter able to sendsignals representing at least one image, a transmission network, areceiver able to receive said signals and an image reproductionprocessor as claimed in claim 6.